1. Field of the Invention
Generally, the present disclosure relates to the field of integrated circuits, and, more particularly, to the manufacture of field effect transistors having a strained channel region caused by a stressed dielectric material formed above the transistor.
2. Description of the Related Art
Integrated circuits typically comprise a large number of circuit elements on a given chip area according to a specified circuit layout, wherein, in complex circuits, the field effect transistor represents one important device component. Generally, a plurality of process technologies are currently practiced, wherein, for complex circuitry based on field effect transistors, such as microprocessors, storage chips and the like, MOS technology is currently one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using CMOS technology, millions of complementary transistors, i.e., N-channel transistors and P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, comprises so-called PN junctions that are formed by an interface of highly doped drain and source regions with an inversely or weakly doped channel region disposed between the drain region and the source region. The conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed above the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on, among other things, the dopant concentration, the mobility of the charge carriers and, for a given extension of the channel region in the transistor width direction, the distance between the source and drain regions, which is also referred to as channel length. Hence, the conductivity of the channel region represents an important factor that substantially affects the performance of the MOS transistors. Thus, the reduction of the channel length, and associated therewith the reduction of the channel resistivity, may be dominant design criteria for accomplishing an increase in the operating speed of integrated circuits.
The shrinkage of the transistor dimensions, however, involves a plurality of issues associated therewith that have to be addressed so as to not unduly offset the advantages obtained by steadily decreasing the channel length of MOS transistors. One problem in this respect is the reduction of the thickness of the gate dielectric layer in order to maintain the desired channel controllability on the basis of increased capacitive coupling. With the thickness of silicon oxide based gate dielectrics approaching 1.5 nanometers and less, the further scaling of the channel length may be difficult due to an unacceptable increase of leakage currents through the gate dielectric. Thus, high-k oxides having a relative dielectric constant of 10 and more, such as, e.g., hafnium oxide, are employed as gate dielectrics, preferably in combination with a thin silicon oxide liner to maintain an appropriate channel/dielectric interface characteristic. Although high-k gate dielectrics allow for a further down-scaling of MOS transistors, there is still a further demand for enhancing performance of the MOS transistors. Furthermore, in view of the problems associated with high-k gate dielectrics, e.g., an insufficient threshold voltage stability, silicon oxide based gate dielectrics are also utilized in state of the art MOS transistors. For this reason, it has been proposed to enhance device performance of the transistor elements not only by reducing the transistor dimensions but also by increasing the charge carrier mobility in the channel region. One efficient approach in this respect is the modification of the lattice structure in the channel region, for instance by creating tensile or compressive strain therein, which results in a modified mobility for electrons and holes, respectively. For example, creating tensile strain in the channel region of a silicon layer having a standard crystallographic configuration may increase the mobility of electrons, which, in turn, may directly translate into a corresponding increase in the conductivity for N-type transistors. On the other hand, compressive strain in the channel region may increase the mobility of holes, thereby providing the potential for enhancing the performance of P-type transistors. Consequently, it has been proposed to introduce, for instance, a silicon/germanium layer or a silicon/carbon layer near the channel region so as to create compressive or tensile stress. In this manner, transistor performance may be considerably enhanced by the introduction of strain-creating materials in the drain and source areas, in particular for P-channel transistors, as, for instance, a silicon/germanium alloy embedded in the drain and source areas has proven to be a very efficient strain-inducing source. To this end, additional epitaxial growth techniques have to be developed and implemented into the process flow so as to form the germanium-containing material.
In other approaches, additionally or alternatively to the above-described concept, a technique is frequently used that enables the creation of desired stress conditions within the channel region of different transistor elements by modifying the stress characteristics of a material that is closely positioned to the transistor structure in order to allow an efficient stress transfer to the channel region. For example, the spacer typically provided at sidewalls of the gate electrodes and the contact etch stop layer that is formed above the basic transistor structure are promising candidates for creating external stress which may then be transferred into the transistor. The contact etch stop layer is, therefore, frequently used since it may be required anyway for controlling an etch process designed to form contact openings to the gate, drain and source terminals in an interlayer dielectric material. The effective control of mechanical stress in the channel region, i.e., an effective stress engineering, may be accomplished for different types of transistors by individually adjusting the internal stress in the contact etch stop layers located above the respective transistor elements so as to position a contact etch stop layer having an internal compressive stress above a P-channel transistor while positioning a contact etch stop layer having an internal tensile strain above an N-channel transistor, thereby creating compressive and tensile strain, respectively, in the respective channel regions.
Typically, the contact etch stop layer is formed by plasma enhanced chemical vapor deposition (PECVD) processes above the transistor, i.e., above the gate structure and the drain and source regions, wherein, for instance, silicon nitride may be used due to its high etch selectivity with respect to silicon dioxide, which is a well-established interlayer dielectric material. Furthermore, PECVD silicon nitride may be deposited with a high intrinsic stress, for example, up to 3 Giga Pascal (GPa) or significantly higher of compressive stress, while stress levels of 1 GPa and higher may be obtained for tensile-stressed silicon nitride materials. The type and the magnitude of the intrinsic stress may be efficiently adjusted by selecting appropriate deposition parameters and selecting appropriate post-deposition treatments based on UV (ultra-violet) treatments, wherein generally process temperatures during deposition and post-deposition treatments are adjusted to 500° C. or less so as to not unduly affect other materials, such as a metal silicide, e.g., a nickel silicide, that is typically formed in the drain and source regions prior to forming the stressed silicon nitride material.
As the contact etch stop layer is positioned close to the transistor, the intrinsic stress may be efficiently transferred into the channel region, thereby significantly improving the performance thereof. Moreover, for advanced applications, the strain-inducing contact etch stop layer may be efficiently combined with other strain-inducing mechanisms, such as strained or relaxed semiconductor materials that are incorporated at appropriate transistor areas in order to also create a desired strain in the channel region. Consequently, the stressed contact etch stop layer is a well-established design feature for advanced semiconductor devices.
An interlayer dielectric, which typically comprises silicon dioxide, is formed on the contact etch stop layer. The interlayer dielectric is planarized to provide a basis for contact elements formed in an opening etched into the interlayer dielectric to provide an electrical connection to the transistor elements, wherein the etch process is stopped in the contact etch stop layer. After removal of the exposed contact etch stop layer regions and exposing contact regions of the transistor elements, the contact elements are formed by depositing an appropriate contact material, such as, for example, tungsten, in the contact opening. In view of the mentioned insufficient threshold voltage stability of high-k MOS transistors and hot carrier degradation of silicon oxide based transistors observed in advanced semiconductor devices, a deuterium (D2) anneal may be performed prior to forming the contact elements to improve the reliability characteristics of MOS transistors. In the annealing process, that may last up to several hours, incorporated deuterium may diffuse to the gate dielectric/channel interface of the transistor. The deuterium is expected to improve the interface quality of the transistor.
As CMOS devices comprise complementary N-channel and P-channel transistors, CMOS devices may comprise transistors with tensile and compressively strained contact etch stop layers which may be formed by a so-called dual stress liner approach.
With reference to FIGS. 1a-1g, a typical integration scheme will now be described in more detail in which a dual stress liner approach and a deuterium anneal is applied.
FIG. 1a schematically illustrates a cross-sectional view of a semiconductor device 100 comprising a substrate 101, above which is provided a semiconductor layer 102, such as a silicon-based semiconductor material whose electronic characteristics are to be enhanced by locally introducing a desired type of strain, as discussed above. The semiconductor layer 102 is laterally divided into a plurality of active regions, which are to be understood as semiconductor regions of the layer 102, in and above which corresponding transistors are to be formed. In the example shown, the first active region 102a is laterally separated from a second active region 102b by an isolation region 102c, which may be provided in the form of a shallow trench isolation. In the example shown, the active region 102a corresponds to an N-channel transistor 150a, while the active region 102b has formed therein and thereon a P-channel transistor 150b. The transistors 150a, 150b comprise gate electrode structures 160, which may have basically the same configuration and which may comprise a gate dielectric material 161, which may comprise silicon oxide and/or a high-k material, and an electrode material 162, which typically includes a semiconductor material such as silicon and/or a metal or metal compound. Usually the overall conductivity of the gate electrode structures 160 is increased by providing a metal silicide 163 on and within the semiconductor material 162. Furthermore, a spacer structure 164 is provided on sidewalls, which may be used for appropriately defining the lateral and vertical profile of drain and source regions 152 and the lateral offset of metal silicide regions 153. Consequently, in a further advanced manufacturing stage, an appropriate strain-inducing mechanism is to be implemented so as to create a desired type of strain, i.e., a tensile strain, in a channel region 151 of the transistor 150a. Similarly, an appropriate strain-inducing mechanism is to be implemented for the transistor 150b so as to induce a compressive strain in the active region 102b. In some advanced approaches, the transistor 150b may comprise an additional strain-inducing mechanism in the form of an embedded silicon/germanium material 154, which is provided in a strained state, thereby also inducing a high compressive strain in the channel region 151 of the transistor 150b. Furthermore, in this manufacturing stage, a thin etch stop layer 111, for instance in the form of a silicon dioxide material, may be formed above the transistors 150a, 150b in order to reduce degradation of sensitive materials of the transistors 150a, 150b upon depositing a highly stressed dielectric material and patterning the same, as will be described later on in more detail. In other strategies (not shown), the etch stop layer 111 may be omitted in order to enhance the overall stress transfer efficiency of a stressed dielectric material still to be formed.
The semiconductor device 100 as illustrated in FIG. 1a may be formed on the basis of the following processes. The active regions 102a, 102b may be formed by appropriately patterning the semiconductor layer 102 and forming the isolation region 102c, followed by the incorporation of appropriate dopant species for adjusting the basic transistor characteristics of the P-channel transistor 150b and the N-channel transistor 150a. To this end, well-established implantation techniques and masking steps are applied. Thereafter, the gate electrode structures 160 are formed, for instance, by depositing appropriate materials for the layers 161 and 162 and subsequently patterning these materials, possibly by providing appropriate hard mask materials and the like, depending on the overall configuration of the gate electrode structures 160 and the patterning strategy to be applied. In sophisticated applications, a length of the gate electrode structures 160, i.e., in FIG. 1a, the horizontal extension of the electrode material 162, is approximately 50 nm and less. Next, drain and source dopant species may be incorporated into the active regions 102a, 102b while forming the spacer structure 164, which may act as an appropriate implantation mask in order to obtain a desired lateral and vertical profile for the regions 152. In some cases when the strain-inducing semiconductor material 154 is to be incorporated into the active region 102b, an appropriate process sequence is supplied after patterning the gate electrode structures 160 and prior to forming the spacer structure 164. To this end, cavities may be etched into the active region 102b while covering the active region 102a and subsequently the material 154 may be grown in the cavities on the basis of selective epitaxial growth techniques. Thereafter, the drain and source regions 152 and the spacer structure 164 may be formed as required. After any high temperature processes, typically the metal silicide materials 153, 163 are formed by applying well-established silicidation techniques wherein a refractory metal is deposited and treated so as to be converted into a metal silicide. For example, frequently nickel, possibly in combination with a certain amount of platinum, is used as the refractory metal, thereby obtaining a highly conductive metal silicide. Next, if required, the etch stop layer 111 may be deposited by any well-established deposition technique.
FIG. 1b schematically illustrates the semiconductor device 100 in a further advanced manufacturing stage. As shown, a strain-inducing dielectric layer 112a, for instance provided in the form of a silicon nitride material, is formed above the transistors 150a, 150b and thus induces a tensile strain component in the active regions 102a, 102b. Furthermore, in the example shown, an additional etch control layer 113, for instance provided in the form of a silicon dioxide material, is formed on the strain-inducing layer 112a, which may be used in a later manufacturing stage upon patterning a further strain-inducing dielectric material still to be formed. Moreover, since the type of internal stress of the layer 112a is inappropriate for the transistor 150b, a resist mask 114 is typically provided so as to enable the removal of an unwanted portion of the layer 112a in a subsequent etch sequence.
The layer 112a may be formed on the basis of well-established plasma enhanced CVD techniques in which, as discussed above, process parameters such as ion bombardment, pressure, composition of precursor gases and the like are appropriately selected so as to deposit the material with a high internal stress level. Furthermore, after deposition of the base material of the layer 112a, further treatment may be performed, for instance by using UV radiation and the like, thereby even further enhancing or generally adjusting the desired magnitude of the internal stress level in the layer 112a. In this manner, a tensile stress level of up to 1.8 GPa or even higher may be achieved while process temperatures may be maintained at or below 500° C., thereby avoiding significant modifications of sensitive materials, such as the nickel silicide 153, 163 and the like. If required, the layer 113 may be deposited, for instance prior to or after any additional treatment of the material 112a, by applying any appropriate deposition technique and the like. Finally, a lithography process may be applied in order to form the resist mask 114 by using well-established strategies.
FIG. 1c schematically illustrates the device 100 in a process environment 120, which is appropriately configured so as to perform a plasma-based etch process 121. Typically, the environment 120 may be provided in the form of an etch chamber in which an appropriate plasma may be established. The plasma is typically established on the basis of oxygen, gas and a CHF gas, which thus provides appropriate radicals in order to efficiently remove material of the layer 112a, while a certain degree of selectivity to silicon dioxide may be achieved, thereby enabling a certain control of the etch process 121. During the process 121, typically a certain amount of the material of the resist mask 114 is also consumed. Subsequently, a further plasma assisted process on the basis of a substantially pure oxygen atmosphere is performed in the same process environment 120 in order to remove the resist mask 114 and other etch byproducts that may have deposited on the surface of the device 100 during the preceding plasma-based etch process.
Typically, after removal from the process environment 120, the further processing is continued by performing a further cleaning process, possibly removing the residues of the etch stop layer 111 from above the transistor 150b, if this layer 111 is provided at all. To this end, wet chemical cleaning recipes may be applied.
FIG. 1 d schematically illustrates the device 100 in a further advanced manufacturing stage. As shown, a further strain-inducing dielectric layer 112b is formed above the transistors 150a, 150b in order to introduce a desired strain in the transistor 150b, for instance in the form of a compressive strain, as discussed above. To this end, the layer 112b may be deposited on the basis of plasma enhanced CVD techniques, possibly in combination with additional radiation treatments and the like, so as to obtain a moderately high internal stress level in the material of the layer 112b. For example, a compressive stress level of 3.5 GPa and even higher may be accomplished on the basis of presently available deposition and treatment recipes for silicon nitride material. Moreover, in order to avoid undue effect of a compressive stress level in the layer 112b on the transistor 150a, i.e., on the previously provided tensile stressed dielectric layer 112a, in a dual stress liner approach, the layer 112b may be removed from above the transistor 150a, which is accomplished by providing a further resist mask 115 and performing a further etch sequence on the basis of similar process parameters as described above with reference to the plasma assisted process 121 (FIG. 1c).
FIG. 1 e schematically illustrates the device 100 within the process environment 120 in a phase when the layer 112b is already removed from above the transistor 150a and the remaining portion of the resist mask 115 is removed, which may be accomplished on the basis of an oxygen plasma 121b, as described above. Next, a further cleaning process is applied in which, if required, the layer 113 may also be removed, thereby preparing the surface of the device 100 for the deposition of an interlayer dielectric material.
FIG. 1f schematically illustrates the device 100 in a further advanced manufacturing stage. An interlayer dielectric layer 180 is formed above the layers 112a, 112b. Any well-established deposition recipes may be applied in order to form an interlayer dielectric material, such as a silicon dioxide material, having a desired thickness in accordance with the overall device requirements. The interlayer dielectric layer 180 may by planarized, e.g., by well-established chemical mechanical polishing techniques. A deuterium (D2) anneal 175 may be performed after deposition of the interlayer dielectric layer 180 as described above to improve the reliability characteristics of the N-channel and P-channel transistors 150a, 150b. A high pressure deuterium (D2) anneal at a temperature in the range of approximately 600-700° C. may be performed for up to several hours to incorporate deuterium and diffuse deuterium close to the gate dielectric/channel interface of the N-channel and P-channel transistors 150a, 150b. 
Thereafter, the interlayer dielectric material is patterned so as to form openings (not shown) therein, wherein the layers 112a, 112b act as efficient etch stop materials. Thereafter, the etch stop layers 112a, 112b are appropriately etched so as to increase a depth of the corresponding contact openings so as to connect to the contact materials 153 and 163, respectively. Thereafter, the contact openings are filled with high conductive material, thereby accomplishing the contact level of the device 100.
Basically, the above-described dual stress liner approach is a very efficient mechanism for inducing a desired type of strain for N-channel transistors and P-channel transistors. In actual integration schemes for providing a deuterium anneal and selectively providing a tensile-stressed dielectric material and a compressively-stressed dielectric material above respective transistor elements, however, the finally observed performance and reliability of these transistors may be significantly less compared to the expected characteristics.
In view of the situation described above, the present disclosure relates to manufacturing techniques in which deuterium is incorporated in a transistor comprising a strain-inducing capping layer so as to obtain superior overall transistor performance and reliability compared to conventional techniques.